1. Field of the Invention
The present invention relates to a multilayer printed circuit board including a power-supply layer where a plurality of power-supply planes are provided, and more particularly, to a multilayer printed circuit board in which generation of radiation noise is suppressed.
2. Description of the Related Art
Conventionally, when designing a multilayer printed circuit board, it is common to provide at least one power-supply layer and at least one ground layer, in addition to a signal layer. Particularly, in an electronic apparatus operating with conventional digital logic circuits, since the power-supply voltage used in a power-supply layer is mainly 5 V, the entire surface of the power-supply layer is, in most cases, constituted by a 5V single 5V-power-supply plane. Recently, however, as digital ICs (integrated circuits) tend to be operated at a lower voltage and to consume lower power, ICs operated with a 5V power supply and ICs operated with a power-supply voltage of 3.3 V or less have come to be mounted, mixed with each other on a single printed circuit board.
As for substrates incorporated in a computer, in order to reduce power consumption by providing a power management function, 5V and 3.3V power supplies are further divided, for example, into 5V-A, 5V-B and 5V-C, and 3.3V-A, 3.3V-B and 3.3V-C, . . . power supplies, respectively, so that many power supplies are often mixed.
As a result, the power-supply layer of a multilayer printed circuit board is not just a single 5V power-supply plane as in the conventional approach, but is divided into 5V and 3.3V power-supply planes, or still more power-supply planes, in order to supply ICs with different required voltages.
A conventional multilayer printed circuit board will now be described with reference to FIGS. 11 through 14.
FIG. 11 is a plan view illustrating the configuration of a first conductive layer in this conventional multilayer printed circuit board.
The first conductive layer comprises a first signal layer 101 provided at the surface side of the multilayer printed circuit board. A first output-side IC 102 operating with a 5V power supply and a second output-side IC 103 operating with a 3.3V power supply are mounted on the first signal layer 101 as electronic devices mounted on the multilayer printed circuit board.
One of the terminals of the first output-side IC 102 is connected to one end of a circuit pattern 104a for a 5V clock signal, where a clock signal having an amplitude of 5 V is transmitted. Another end of the circuit pattern 104a for the 5V clock signal is connected to a through-hole 105 subjected to interlayer connection to one end of a circuit pattern 104b for the 5V clock signal provided on a second signal layer 116 (see FIG. 14). Another terminal of the first output-side IC 102 is connected to a through-hole 106 subjected to interlayer connection to a power supply layer 112 (see FIG. 13) in order to supply the first output-side IC 102 with a power-supply voltage of 5V.
One of the terminals of the second output-side IC 103 is connected to one end of a circuit pattern 107 for a 3.3V clock signal where a clock signal having an amplitude of 3.3 V is transmitted. Another end of the circuit pattern 107 for the 3.3V clock signal is connected to a through-hole 108 connected to an input terminal of a second input-side IC mounted on the second signal layer 116 (see FIG. 14). Another terminal of the second output-side IC 103 is connected to a through-hole 109 subjected to interlayer connection to the power-supply layer 112 in order to supply the second output-side IC 103 with a suitable power-supply voltage.
FIG. 12 is a plan view illustrating the configuration of a second conductive layer in the conventional multilayer printed circuit board.
The second conductive layer comprises a ground layer 110 provided in an inner layer below the first signal layer 101. The ground layer 110 is provided in the form of a uniform plane.
FIG. 13 is a plan view illustrating the configuration of a third conductive layer in the conventional multilayer printed circuit board.
The third conductive layer comprises the power-supply layer 112 provided in an inner layer below the ground layer 110. A 5V-power-supply plane 113 and a 3.3V-power-supply plane 114 are provided on the power-supply layer 112. The above-described through hole 106 is connected to the 3.3V-power-supply plane 114.
FIG. 14 is a plan view illustrating the configuration of a fourth conductive layer in the conventional multilayer printed circuit board.
The fourth conductive layer comprises the second signal layer 116 provided at the back of the multilayer printed circuit board. A first input-side IC 117 operating with a 5V power supply and a second input-side IC 118 operating with a 3.3V power supply are mounted on the second signal layer 116 as electronic devices mounted on the multilayer printed circuit board.
One of the terminals of the first input-side IC 117 is connected to one end of the circuit pattern 104b for the 5V clock signal, where the clock signal having the amplitude of 5 V is transmitted. Another end of the circuit pattern 104b for the 5V clock signal is connected to the above-described through-hole 105. Another terminal of the first input-side IC 117 is connected to a through-hole 119 subjected to interlayer connection to the power-supply layer 112 in order to supply the first input-side IC 117 with a power-supply voltage of 5 V.
One of the terminals of the second input-side IC 118 is connected to the above-described through-hole 108. Another terminal of the second input-side IC 118 is connected to a through-hole 120 subjected to interlayer connection to the power-supply layer 112 in order to supply the second input-side IC 118 with a power-supply voltage.
In the above-described conventional multilayer printed circuit board, circuit patterns for various signals (not shown) including the circuit patterns 104a, 104b and 107 for respective clock signals are provided on the first signal layer 101 and the second signal layer 116. The circuit patterns 104a and 104b for the 5V clock signal are connected to each other between the first signal layer 101 and the second signal layer 116.
Thus, a microstrip structure is provided between the circuit pattern 107 for the 3.3V clock signal provided on the first signal layer 101, and the ground layer 110, and a microstrip structure is also provided between the circuit pattern 104b for the 5V clock signal provided on the second signal layer 116, and the power supply layer 112 in a state in which the circuit pattern 104b for the 5V clock signal crosses over the 3.3V-power-supply plane 114.
In the configuration where the ground layer 110 is provided immediately below the circuit pattern 107 for the 3.3V clock signal on the first signal layer 101, capacitive coupling and inductive coupling between the circuit pattern 107 for the 3.3V clock signal and the ground layer 110 are large. Accordingly, when a signal current flows from the second output-side IC 103 to the second input-side IC 118 via the circuit pattern 107 for the 3.3V clock signal and the through-hole 108, a return current caused by the signal current rectilinearly flows through a current path 111 on the ground layer 110 immediately below the circuit pattern 107 for the 3.3V clock signal.
In the configuration that the power-supply layer 112 is provided immediately below the circuit pattern 104b for the 5V clock signal on the second signal line 116, capacitive coupling and inductive coupling between the circuit pattern 104b for the 5V clock signal and the power-supply layer 112 are large. Accordingly, when a signal current flows from the first output-side IC 102 to the first input-side IC 117 via the through-hole 105 and the circuit pattern 104b for the 5V clock signal, a return current caused by the signal current flows through a current path 115 on the power-supply layer 112. Since the circuit pattern 104b for the 5V clock signal is provided so as to cross over the 3.3V-power-supply plane 114, the return current detours around the 3.3V-power-supply plane 114 instead of rectilinearly flowing immediately below the circuit pattern 104b for the 5V clock signal.
Next, a description will be provided of another conventional multilayer printed circuit board, with reference to FIGS. 15 through 20.
FIG. 15 is a plan view illustrating the configuration of a first conductive layer in this conventional multilayer printed circuit board.
The first conductive layer comprises a first signal layer 201 provided at the surface side of the multilayer printed circuit board. A first output-side IC 202 operating with a 5V power supply and a second output-side IC 203 operating with a 3.3V power supply are mounted on the first signal layer 201, as electronic devices mounted on the multilayer printed circuit board.
One of the terminals of the first output-side IC 202 is connected to one end of a circuit pattern 204a for a 5V clock signal where a clock signal having an amplitude of 5 V is transmitted. Another end of the circuit pattern 204a for the 5V clock signal is connected to a through-hole 205a subjected to interlayer connection to one end of a circuit pattern 204b for the 5V clock signal provided on a third signal layer 218 (see FIG. 19). Another terminal of the first output-side IC 202 is connected to a through-hole 206 in order to supply the first output-side IC 202 subjected to interlayer connection to a power-supply layer 214 with a power-supply voltage of 5 V.
One of terminals of the second output-side IC 203 is connected to a through-hole 209 subjected to interlayer connection to one end of a circuit pattern 207 for a 3.3V clock signal provided on a second signal layer 211 (see FIG. 16). Another terminal of the second output-side IC 203 is connected to a through-hole 210 subjected to interlayer connection to a power-supply layer 214 (see FIG. 18) in order to supply the second output-side IC 203 with a power-supply voltage.
FIG. 16 is a plan view illustrating the configuration of a second conductive layer in the above-described multilayer printed circuit board.
The second conductive layer comprises the second signal layer 211 provided in an inner layer below the first signal layer 201. The circuit pattern 207 for the 3.3V clock signal where a clock signal having an amplitude of 3.3 V is transmitted is provided on the second signal layer 211. One end of the circuit pattern 207 for the 3.3V clock signal is connected to the above-described through-hole 209. Another end of the circuit pattern 207 for the 3.3V clock signal is connected to a through-hole 208 where an input terminal of a second input-side IC 221 mounted on a fourth signal layer 219 (see FIG. 20) is connected.
FIG. 17 is a plan view illustrating the configuration of a third conductive layer in the above-described multilayer printed circuit board.
The third conductive layer comprises a ground layer 212 provided in an inner layer below the second signal layer 211.
FIG. 18 is a plan view illustrating the configuration of a fourth conductive layer in the above-described multilayer printed circuit board.
The fourth conductive layer comprises a power-supply layer 214 provided in an inner layer below the ground layer 212. A 5V-power-supply plane 215 and a 3.3V-power-supply plane 216 are provided on the power-supply layer 214. The above-described through-hole 206 is connected to the 3.3V-power-supply plane 216, and the through-hole 210 is connected to the 3.3V-power-supply plane 216.
FIG. 19 is a plan view illustrating the configuration of a fifth conductive layer in the above-described multilayer printed circuit board.
The fifth conductive layer comprises a third signal layer 218 provided in an inner layer below the ground layer 212. The circuit pattern 204b for the 5V clock signal where a clock signal having an amplitude of 5 V is transmitted is provided on the third signal layer 218. One end of the circuit pattern 204b for the 5V clock signal is connected to the above-described through-hole 205a. Another end of the circuit pattern 204b for the 5V clock signal is connected to a through-hole 205b connected to one of terminals of a first input-side IC 220 mounted on the fourth signal layer 219 (see FIG. 20).
FIG. 20 is a plan view illustrating the configuration of a sixth conductive layer in the above-described multilayer printed circuit board.
The sixth conductive layer comprises the fourth signal layer 219 provided at the back of the multilayer printed circuit board. The first input-side IC 220 operating with a 5V power supply and a second input-side IC 221 operating with a 3.3V power supply are mounted on the fourth signal layer 219, as electronic devices mounted on the multilayer printed circuit board.
One of the terminals of the first input-side IC 220 is connected to the through-hole 205b connected to one end of the circuit pattern 204b for the 5V clock signal. Another terminal of the first input-side IC 220 is connected to a through-hole 222 subjected to interlayer connection to the power-supply layer 214 in order to supply the first input-side IC 220 with a power-supply voltage of 5 V.
One of the terminals of the second input-side IC 221 is connected to the above-described through-hole 208. Another terminal of the second input-side IC 221 is connected to a through-hole 223 subjected to interlayer connection to the power-supply layer 214 in order to supply the second input-side IC 221 with a power-supply voltage.
In the above-described conventional multilayer printed circuit board, circuit patterns for various signals (not shown) including the circuit patterns 204b and 207 for respective clock signals are provided on the second signal layer 211 and the third signal layer 218.
Thus, a microstrip structure is provided between the circuit pattern 210 for the 3.3V clock signal provided on the second signal layer 211, and the ground layer 212, and a microstrip structure is also provided between the circuit pattern 204b for the 5V clock signal provided on the third signal layer 118, and the power supply layer 214 in a state in which the circuit pattern 204b for the 5V clock signal crosses over the 3.3V-power-supply plane 216.
In the configuration where the ground layer 212 is provided immediately below the circuit pattern 207 for the 3.3V clock signal on the second signal layer 211, capacitive coupling and inductive coupling between the circuit pattern 207 for the 3.3V clock signal and the ground layer 212 are large. Accordingly, when a signal current flows from the second output-side IC 203 to the second input-side IC 222 via the circuit pattern 207 for the 3.3V clock signal and the through-hole 208, a return current caused by the signal current rectilinearly flows through a current path 213 on the ground layer 212 immediately below the circuit pattern 207 for the 3.3V clock signal.
In the configuration where the power-supply layer 213 is provided immediately below the circuit pattern 204b for the 5V clock signal on the third signal line 218 so as to face it, capacitive coupling and inductive coupling between the second signal layer 218 and the power-supply layer 214 are large. Accordingly, when a signal current flows from the first output-side IC 202 to the first input-side IC 220 via the through-hole 205a, the circuit pattern 204b for the 5V clock signal and the through hole-205b, a return current caused by the signal current flows through a current path 217 on the power-supply layer 214. Since the circuit pattern 204b for the 5V clock signal is provided so as to cross over the 3.3V-power-supply plane 216, the return current detours around the 3.3V-power-supply plane 216 instead of rectilinearly flowing immediately below the circuit pattern 204b for the 5V clock signal.
In the above-described multilayer printed circuit boards, since a microstrip structure is provided between the signal layer and the power supply layer or the ground layer, the signal transmission line characteristic impedance is constant. As a result, a high-quality transmission waveform is obtained, and a signal, such as a clock signal or the like, which serves as a radiation source having the largest electromagnetic radiation noise from the printed circuit board, is transmitted with high reliability in a state in which the electromagnetic radiation noise is suppressed.
However, in the above-described conventional multilayer printed circuit boards, since the circuit pattern for the clock signal is provided so as to cross over the power-supply plane having a power-supply voltage different from the voltage of a signal transmitted through the circuit pattern for the clock signal, a return current flows in the power-supply layer so as to detour around the power-supply plane.
Since the return current flows with a large loop instead of flowing through the shortest rectilinear distance, electromagnetic radiation noise radiated from the printed circuit board increases in proportion to the length of the loop. As a result, control values provided by organizations of various countries, such as VCCI (Voluntary Control Council for Interference by Data Processing Equipment and Electronic Office Machines), FCC (Federal Communications Commission), CISPR (International Special Committee on Radio Interference) and the like, cannot, in some cases, be met.